In order to explain the background of the present invention, reference will be particularly made to FIG. 1:
In FIG. 1, the reference numeral 1 designates a semiconductor device with a redundancy circuit. The numerals 2 and 3 designate external input terminals of the semiconductor device 1. The numerals 4 and 5 designate input protection circuit portions. The input protection circuit portion 4 is constituted by MOS gates 4a, 4b and the resistances 4c, 4d. The numeral 6 designates a redundancy distinction circuit for distinguishing the use or non-use of the redundancy circuit. This redundancy distinction circuit 6 is constituted by a fuse 6a and a MOS gate 6b. The numeral 7 designates a ground line of the semiconductor device.
The judgement as to whether the redundancy circuit is used or not in this prior art device is conducted as follows:
The faulty portion generated due to the contaminations and the crystal defects of the wafer is replaced by the corresponding redundancy circuit. This technique is widely accepted as a redundancy circuit technique in a wafer production process for semiconductor devices with the advance of high integration of the semiconductor devices. The information as to whether the redundancy circuit is used or not in the semiconductor device is required in evaluating and analyzing the semiconductor device, and it can be easily recognized from the external input terminal 2. In a semiconductor device with a redundancy circuit the fuse 6a is cut off by an apparatus for replacing the redundancy circuit in a redundancy circuit replacement process. The cutting off of the fuse is conducted by blowing off the fuse by using a laser beam or a large current. The existence or non-existence of the fuse can be easily recognized by conducting a measurement against the external input terminal 2 as in the following:
The MOS gates 4b, 6b lare turned on by applying a negative voltage to the external input terminal 2, and then a current is flows out to the external input terminal 2 from the ground line 7 through the MOS gate 4b and the resistance 4c. When the fuse 6a is not blown off, a current also flows out to the external input terminal 2 from the ground line 7 through the MOS gate 6b, the fuse 6a, and the resistance 4c. That is, the value of the current flowing out to the external input terminal 2 is changed in accordance with the fuse 6a being cut off or not, and the current when being cut off becomes about half of that when not being cut off. It is easily possible to judge the use or non-use of the redundancy circuit by measuring this value by an inspection apparatus for the semiconductor device. The measurement is generally called a pin contact test, which is a fundamental one among the semiconductor device checking items, and the measurement time therefor is a short time of several milli-seconds.
Each semiconductor device on a wafer after a wafer process is executed thereto is wafer-tested. In this wafer test, the semiconductor device is again subjected to a test which is more severe than that executed in judging the capability of a redundancy circuit replacement. The function test items executed in the redundancy circuit replacement process are usually executed also in the wafer test items. That is, the similar function test items are executed two times regardless of a good or a bad product.
In this prior art semiconductor device with a redundancy circuit the use or non-use of the redundancy circuit can be detected directly. However, it is necessary to execute a function test again in order to judge the goodness or badness of the semiconductor device, thereby requiring a time for a bad product test in a wafer test as the next inspection process. The time required for this bad product test is about 0.5 seconds in a 1 Mbit RAM assuming that 1 bit is tested in 500 nsec.
Another prior art redundancy secured semiconductor device is disclosed in an article "A Fault-Tolerant 64 K Dynamic RAM" by R.P. Cenker et al. ISSCC 79/Thursday, February 15, '79. In this device, a poly-silicon fuse which is blown off by a laser beam is inserted at the corresponding address line so as to enable the replacement of the faulty cell by the redundancy cell.
The other prior art redundancy secured semiconductor device is disclosed in an article "Redundancy Techniques for Fast Static RAMs" by K. Kokkonen et al., ISSCC 81/Wednesday, Feb., '81. In this device, a poly-silicon fuse which is electrically blown off from the outside of the device is inserted at the corresponding address line so as to enable the replacement of the faulty cell by the redundancy cell.